The present technology relates to a driving circuit that performs gray-scale display by pulse-width modulation (PWM), and a display including the driving circuit. In addition, the present technology relates to a method of driving the above-mentioned display.
In digital displays that perform gray-scale display by PWM, a gray-scale display method as illustrated in FIG. 5 is used in an exemplary case of 5 bits (32 gray-scale levels), for example. Specifically, as illustrated in FIG. 5, with 1 bit data of several ms width taken as a unit for example, five pieces of data having a period length ratio of 1:2:4:8:16 are prepared, and 32 gray-scale levels are expressed by a combination of these five pieces of data.
FIG. 6 shows a relationship between signal data of sequential scanning and selection pulses applied to scan lines in known general digital driving. FIG. 6 shows a case of three scan lines for convenience of description. As is clear from FIG. 6, in a known general digital display, one frame period (1F) is divided into subfields SF1 to SF5 corresponding to respective bits (in this example, a first bit to a fifth bit) of gray-scale data, and having period lengths commensurate with the weights of the corresponding bits. In this configuration, an electro-optical device of a pixel is turned on or off according to the corresponding bit in each of the subfields SF1 to SF5, and thus a ratio of ON period or OFF period to 1F is stepwisely controlled. Further, data is written in pixels through scan lines by line-sequential scanning in each of the subfields SF1 to SF5. It is to be noted that, information on the above-mentioned digital driving is described in Japanese Unexamined Patent Application Publication No. 2006-343609 and the like.